1. Field of Invention
This invention relates to a mask exposure method used in the production of semiconductor devices. This invention also relates to a reticle mask used in the method. This invention further relates to a semiconductor product wafer produced by the method. This invention also relates to a method of producing semiconductor device chips.
2. Description of Related Art
Semiconductor devices, such as semiconductor integrated circuits, are generally produced by repeatedly exposing a semiconductor wafer through a mask pattern on a reticle using an exposing apparatus, such as a stepper, thereby forming a plurality of exposed areas arranged on the entire surface of the semiconductor wafer. The image of the mask pattern is printed on a resist layer applied on the surface of the semiconductor wafer, and developed to form a resist pattern, which is used as a mask for, for example, etching a layer formed on the surface of the wafer. By repeating these processes, a plurality of semiconductor device chips is produced on entire surface of the wafer. The semiconductor devices chips are separated into individual semiconductor devices at scribe lines between the chips and encapsulated into packages.
Typically, a reduction-type exposing apparatus is used to expose semiconductor wafers. Therefore, the size of the mask patterns on the reticle is several times the size of the actual semiconductor device patterns formed on the semiconductor wafer.
In addition to these actual devices, test devices for measuring electrical characteristics are also formed on semiconductor wafers. These test devices are called test element groups (TEGs) and are formed, for example, in the scribe lines.
Japanese Unexamined Patent Application Publication Nos. 5-291106 and 10-312049 disclose exposure processes of chip patterns. In these processes, a semiconductor chip pattern (LSI pattern) and a TEG pattern are arranged on the same reticle. Required positions of the wafer are exposed through the TEG pattern and the other positions are exposed through the chip pattern. To expose through the TEG pattern, mask blinds of the stepper cover the chip pattern on the reticle so that only the TEG pattern is projected onto the wafer. The TEG pattern is covered to expose through the chip pattern.
A serious concern in semiconductor production is to increase the number of semiconductor device chips produced on one semiconductor wafer. A countermeasure is narrowing the scribe lines. This method is particularly effective in producing semiconductor devices with small chip dimensions, such as 1 mmxc3x971 mm. A plurality of mask patterns for such small semiconductor device chips are closely arranged with narrow scribe lines of, for example, 50 xcexcm (the width when exposed on the wafer) on the same reticle so that the size of the entire mask pattern substantially corresponds to a field size, for example, 20 mmxc3x9720 mm that can be exposed at once by the exposing apparatus. The number of the chips formed by an exposure step and the total number of the chips formed on the entire wafer can be increased. Because the TEG patterns and alignment marks for the exposing apparatus cannot be included within the width of such narrow scribe lines, regions corresponding to one to several semiconductor chips on the mask pattern are allocated to the TEG patterns and the alignment marks.
When the above exposure step, however, is repeated over the entire surface of the semiconductor wafer, a plurality of exposed areas, each composed of a device region including a plurality of semiconductor device chips and a TEG region, is formed on the semiconductor wafer. In order to increase the number of the device chips produced on one wafer, it is preferable that the number of the TEG regions on one wafer be minimized as much as possible, for example, to one to several, by producing the TEG regions in only specific positions.
In the above-described process using the mask blinds, however, the step pitch in the exposed areas arranged on the wafer surface cannot be maintained constant, when the device region and the TEG region have different sizes.
Thus, the distances between alignment marks for use in a laser-trimming step, each provided at a specific position in each device region, are different. Therefore, the laser-trimming step requires complicated treatment, such as combining a plurality of map layouts, or splitting in a plurality of steps on each wafer. Moreover, 5 to 10% of the chips on the periphery of the wafer cannot be treated depending on the laser-trimming apparatuses. A process for measuring electrical characteristics is also complicated due to the irregular distances between the TEG regions.
Accordingly, it is an object of this invention to provide an exposure method capable of arranging exposed areas with fixed pitches even when TEG regions are formed only at several positions on a semiconductor wafer.
It is another object of this invention to provide a reticle mask used in the exposing method.
According to one aspect of this invention, an exemplary method of fabricating semiconductor devices comprises: applying a resist layer on a surface of a semiconductor wafer; forming a plurality of exposed areas in the resist layer arranged in rows and columns with fixed pitches, the exposed areas including a plurality of first exposed areas each including a device region, and at least one second exposed area including a portion of the device region and a TEG region.
Preferably, the device region of the first exposed areas includes a predetermined number of rows of exposed device chip patterns and the portion of the device region of the second exposed area includes a number of rows of the exposed device chip patterns that is less than the predetermined number of rows.
Preferably, each of the first exposed regions is formed by a single exposure.
Preferably, the first and the second exposed areas are formed using a common reticle having a device pattern region to form the device region and a having TEG pattern region to form the TEG region.
Preferably, the second exposed area is formed by a first exposure of the resist layer through a portion of the device pattern region and by a second exposure of the resist layer through the TEG pattern region of the common reticle.
Preferably, the TEG pattern region of the common reticle includes a blank zone, and a defective pattern formed by the first exposure is erased by the second exposure through the blank zone, or the second exposure through the blank zone prevents formation of a defective pattern by the first exposure.
Preferably, at least one of the first exposed areas is formed by exposing the resist layer through both the device pattern region and the TEG region of the common reticle so that the TEG region of the second exposed area adjacent to the at least one of the first exposed areas is formed simultaneously.
According to another aspect of this invention, an exemplary method of fabricating semiconductor devices comprises: setting a reticle having a device pattern region and a TEG pattern region in an exposing apparatus; positioning a semiconductor wafer having a resist layer on the semiconductor wafer in the exposing apparatus; and forming an exposed area in the resist layer by a first exposure through a portion of the device pattern region of the reticle and by a second exposure through the TEG pattern region of the reticle, wherein a defective pattern formed by the first exposure is erased by the second exposure, or the second exposure prevents formation of a defective pattern by the first exposure.
Preferably, the TEG pattern region of the reticle includes a blank zone and the second exposure though the blank zone erases or prevents the formation of the defective pattern.
Preferably, the device pattern region of the reticle includes a predetermined number of rows of device chip patterns and the portion of the device pattern region includes a number of rows of the device chip patterns that is less than the predetermined number of rows and a portion of an adjacent row of the device chip patterns.
According to another aspect of this invention, an exemplary reticle for use in an exposing apparatus comprises: a rectangular pattern forming area on a surface of a substrate, the pattern forming area having a side; and a device pattern region and a TEG pattern region arranged within the pattern forming area along a first direction perpendicular to the side of the pattern forming area, wherein the TEG pattern region includes a blank zone extending along a substantial length of the side of the pattern forming area.
Preferably, the TEG pattern region further includes a blind zone extending along a substantial length of a boundary between the device pattern region and the TEG pattern region in parallel with the side of the pattern forming area
Preferably, the device pattern region includes a plurality of rows of device chip patterns for producing semiconductor device chips. The rows of the device chip patterns are aligned in the first direction.
Preferably, a width of scribe lines between the rows of the device chip patterns is smaller than an alignment error of a mask blind of the exposing apparatus.
Preferably, a dimension of the blank zone along the first direction is at least twice of an alignment error of a mask blind of the exposing apparatus.
According to another aspect of this invention, an exemplary semiconductor product wafer comprises: a plurality of patterned areas arranged vertically and horizontally with fixed pitches on a surface of the wafer, the patterned areas including a plurality of first patterned areas each including a device region and at least one second patterned area including a portion of the device region and a TEG region.
Preferably, the device region in each of the first pattern areas includes a predetermined number of rows of device chips, and the portion of the device region of the second patterned area includes a number rows of the device chips that is less than the predetermined number of rows of the device chips.
Preferably, a width of a scribe line between the rows of the semiconductor device chips is the same as that of a scribe line between the TEG region and an adjacent one of the rows of the device chips in the second patterned area.
Preferably, the TEG region is smaller than the portion of the device region.
According to another aspect of this invention, an exemplary method of producing semiconductor device chips comprises: forming a plurality of patterned areas arranged vertically and horizontally with fixed pitches on a surface of a semiconductor wafer, the patterned areas including a plurality of first patterned areas each including a device region and at least one second patterned area including a portion of the device region and a TEG region, such that each of the device regions and the portion of the device region includes at least one device chip, and at least selected ones of the patterned areas include alignment marks at a fixed relative position within the respective patterned areas; and directing an energy beam onto selected ones of the device chips by using the alignment marks as positional references and trimming the selected ones of the device chips using the energy beam.
Preferably, the device region in each of the first patterned areas includes a predetermined number of rows of the device chips, and the portion of the device region of the second patterned area includes a number of rows of the device chips that is less than the predetermined number of rows of the device chips.
Preferably, the plurality of patterned areas includes at least our, incomplete patterned area on the periphery of the wafer that includes at least one device chip; and the directing directs the energy beam onto the device chip in the incomplete patterned area using the alignment marks in at least one of the first and the second patterned areas as the positional references.
Herein, a region of a mask pattern on a reticle for producing semiconductor device chips is referred to as a xe2x80x9cdevice pattern region,xe2x80x9d and a region of a mask pattern for producing TEGs is referred to as a xe2x80x9cTEG pattern region.xe2x80x9d An area on a semiconductor wafer exposed through the reticle is referred to an xe2x80x9cexposed area.xe2x80x9d In the exposed area, a latent image corresponding to the mask pattern on the reticle is formed in a resist layer on the surface of the semiconductor wafer. The latent image is developed to form a resist pattern, which is used, for example, as a mask for etching. The exposed area includes a device region exposed through the device pattern region on the reticle and/or a TEG region exposed through the TEG pattern region on the reticle. In the exposing process of this invention, a plurality of exposed areas is arranged in rows and columns with fixed pitches in horizontal and vertical directions on the semiconductor wafer. Each exposed area may be formed by a single exposure step or a plurality of exposure steps.
As the simplest method for achieving a shot layout (arrangement of exposed areas) with constant step pitches, two separate reticles can be used. That is, a first reticle including a device pattern region is used to form first exposed areas including only the device regions. A second reticle including a device pattern region and a TEG pattern region and having the same dimension as that of the first reticle is used to form second exposed areas each including both the device region and the TEG region. This method, however, requires two reticles for each layer in production of the semiconductor devices. Many sets of these reticles must be prepared and exchanged frequently in the production of advanced semiconductor devices, resulting in high cost and low production efficiency.
It is, therefore, preferable that the device regions and the TEG regions be exposed using a common reticle including both a device pattern region having an arrangement of a plurality of semiconductor device chip mask patterns and a TEG pattern region. In this case, exposure must be performed, for example, using mask blinds of the exposing apparatus for covering undesired portions of the reticle. The accuracy of alignment of the mask blinds, however, is low, resulting in a positioning error. The positioning error distributes statistically. Typically, three-times of the standard deviation (3"sgr") of the positioning error is approximately 100 xcexcm on the wafer. Therefore, the exposure method should accept an alignment error of the mask blinds of approximately 100 xcexcm on the wafer.
When exposure is performed using only the device pattern region, a blind zone having an adequate width provided at a boundary between the device pattern region and the TEG pattern region absorbs the alignment error of the mask blind.
To form a second exposed area containing both the device region and the TEG region, a portion of the device pattern region on the reticle should be covered so that a total dimension of the second exposed area is equal to that of the first exposed area containing only the device region. Therefore, the mask blinds should be used to expose through only a portion of the device pattern region and the TEG region. However, when the exposure is performed by covering a portion of the device pattern region, a defective pattern in which only a portion of the device chip pattern is printed is formed on the semiconductor wafer due to an alignment error of the mask blind at the boundary between a region to be exposed and a region not to be exposed in the device pattern region.
A possible method to prevent the formation of such a defective pattern is providing a blind zone within the device pattern region. This method, however, requires a sufficiently wide scribe line at the boundary, resulting in a reduced number of semiconductor chips producible on one semiconductor wafer.
In a preferred embodiment, a reticle is used in which both a device pattern region and a TEG pattern region are included, and a blind zone and a blank zone are provided in the TEG pattern region. More specifically, the blind zone is provided at one side of the TEG pattern region on the device pattern region side, and the blank zone is provided at the other side of the TEG pattern region away from the device pattern region. The width of the blind zone and the width of the blank zone may be appropriately determined depending on the alignment accuracy of the mask blind.
Using this reticle, first exposure steps of exposing the resist layer through only the device pattern region, second exposure steps of exposing through both the device pattern region and the TEG pattern region, and third exposure steps of exposing through only a portion of the device pattern region are repeated in an appropriate combination. By these exposure steps, first exposed areas including only the device region and second exposed areas, each including both the portion of the device region and the TEG region and having the same dimension as the first exposed area, can be formed on the semiconductor wafer. Because the dimension of the first exposed area and that of the second exposed area are the same, arbitrary numbers of the first and the second exposed areas can be arranged on the surface of the semiconductor wafer in rows and columns with fixed vertical and horizontal pitches.
The light passing through the blank zone in the TEG pattern region in the subsequent second exposure step erases a defective pattern formed on the semiconductor wafer in the third exposure step. Alternatively, the light passing through the blank zone in the second exposure step prior to the third exposure step preliminarily exposes a region where, without the second exposure step, the defective pattern would be formed, and prevents the formation of the defective pattern in the third exposure step.